1. Field of the Invention
The present invention relates to an alignment mark and a method for manufacturing a semiconductor device having the same. More particularly, the present invention relates to a method for forming an alignment mark that is appropriate for manufacturing a semiconductor device having a silicon-on-insulator substrate.
2. Description of the Related Art
Highly integrated semiconductor devices are required to rapidly process massive amounts of information. To meet the requirement, semiconductor devices need to operate at high speed. Accordingly, various technologies have developed for manufacturing a semiconductor device having a rapid operation speed.
A technology in which a silicon-on-insulator (SOI) substrate is used is proposed. The SOI substrate has a single crystalline silicon layer that is formed on a buried oxide (BOX) layer. When a semiconductor device is formed on the SOI substrate, the semiconductor device, that is an SOI device, is divided into unit elements by the BOX layer, thereby preventing latch-up of a transistor in the semiconductor device and reducing parasitic capacitance. Thus, the SOI device may have reduced power consumption and a rapid operation speed compared to a device that is formed on a bulk silicon substrate.
Processes for manufacturing the SOI device require an alignment mark for patterning various layers. The alignment mark precisely aligns an SOI substrate with a mask used in an exposure process of a photoresist layer. The alignment mark may be formed on a scribe lane positioned between chips.
FIGS. 1A to 1C are cross sectional views illustrating a conventional method for forming an alignment mark on an SOI substrate.
Referring to FIG. 1A, an SOI substrate 10 has a silicon substrate 10a, a buried oxide (BOX) layer 10b and a silicon layer 10c. A typical isolation process is performed on the SOI substrate 10 to form an active region having an exposed surface and a field region having a field oxide layer 15 on the SOI substrate 10. The field oxide layer 15 contacts the BOX layer 10b. 
The SOI substrate 10 is divided into device area D in which a semiconductor chip is formed and scribe lane area S positioned between the device areas D. Test chips, an alignment mark, etc., are formed on the scribe lane area S by successive processes.
The alignment mark includes an alignment pattern and an alignment groove adjacent to the alignment pattern. An aligner of exposure equipment recognizes the alignment mark by detecting depth of the alignment groove and an inclined angle of a sidewall of the alignment pattern in an exposure process, thereby aligning the SOI substrate 10. The closer the inclined angle of the sidewall approaches a right angle, the more readily the aligner recognizes the alignment mark.
Referring to FIG. 1B, a photoresist pattern 20 selectively exposing the scribe lane region S is formed on the SOI substrate 10. The exposed surface of the active region is dry etched using the photoresist pattern 20 as a mask and using an etchant that has an etching selectivity relative to silicon oxide, which is higher than that of silicon. In particular, the field oxide layer 15 positioned in the scribe lane region S and the BOX layer 10b beneath the field oxide layer 15 are etched using the etchant. In the etching process, the silicon layer 10c is rapidly etched compared to the field oxide layer 15 and the BOX layer 10b. Accordingly, a stepped structure having the alignment pattern 25 and the alignment groove is formed on the active region and the field region. The alignment pattern 25 is positioned in the active region and the alignment groove is positioned in the field region.
To recognize the alignment mark by the exposure equipment, the alignment pattern has a high height. Thus, the field oxide layer 15 and the BOX layer 10b are removed by a thickness of about thousands of angstroms (Å). Here, the silicon layer 10c is simultaneously removed by a thickness of about hundreds of angstroms.
When the silicon layer 10c has a thick thickness, a parasitic capacitance may greatly increase. To reduce the parasitic capacitance, the thickness of the silicon layer 10c has been thinned. In general, when the silicon layer 10c has a thickness of about hundreds of angstroms, the silicon layer 10c is entirely removed by the etching process to form the alignment pattern 25 that only has the BOX oxide layer 15.
Referring to FIG. 1C, the photoresist layer 20 is stripped using a stripping solution. A cleaning process using a cleaning solution is performed on the SOI substrate 10.
The alignment pattern 25 only having the BOX layer 15 may be attacked by the stripping solution and the cleaning solution. Particularly, since an upper edge portion of the alignment pattern 25a may be more attacked by the solutions, the upper edge portion of the alignment pattern 25a may be more crushed compared to other portions of the alignment pattern 25a. 
It may be difficult to recognize the crushed alignment pattern 25a by the exposure equipment. As a result, a photoresist pattern used in the exposure process may be mis-aligned due to incorrectly recognizing the alignment mark or its location caused by the crushed alignment pattern 25a. Even further, the exposure process may be not carried out owing to recognition failure caused by the crushed alignment pattern 25a. 